1. Field of the Invention
The present invention relates to a semiconductor device that simultaneously activates more word lines during a refresh operation than during a normal operation.
2. Description of Related Art
The storage capacities of semiconductor memory devices as typified by a DRAM (Dynamic Random Access Memory) are increasing year by year, and accompanying such increases the area occupied by a single memory cell is being reduced more and more. Consequently, it is difficult to manufacture all the memory cells without any defects, and in practice a large number of defective memory cells are produced in the manufacturing stage. The addresses of defective memory cells are detected by an operation test that is conducted when semiconductor memory devices are in a wafer state, and are written in a non-volatile memory element such as a fuse circuit. Subsequently, when an access is requested to an address of a defective memory cell, an alternate access is made to a redundant memory cell and not to the defective memory cell, and thus the operation to access the relevant address is remedied.
A memory cell of a DRAM comprises one cell capacitor and one cell transistor, and stores information by means of a charge amount stored in the cell capacitor. Charging and discharging with respect to the cell capacitor is controlled by the cell transistor that is connected to a word line. When the cell transistor is turned on, a storage electrode of the cell capacitor is connected to a bit line and thus reading out or writing of information can be performed.
Because a memory cell of a DRAM stores information based on the amount of a charge stored in a cell capacitor in this way, the information will be eliminated by a leak current unless a refresh operation is performed regularly. Thus, it is necessary to refresh all memory cells before the information is eliminated by a leak current, and a cycle (=tREF) at which all memory cells are to be refreshed is defined by the standards as, for example, 64 msec. The standard for this cycle is described in JP2003-187578A.
For many DRAMs, a method is adopted that reduces the frequency of refresh operations by simultaneously activating a larger number of word lines at the time when a refresh operation is performed than at the time when a normal operation is performed. According to this method, at the time when a refresh operation is performed, for example, by disabling the most significant bit of the row address, it is possible to simultaneously activate twice the number of word lines compared to the time when normal access is executed. In this case, how to handle the refresh operation when a refresh address is the address of a defective memory cell is a problem. More specifically, at the time when a refresh operation is performed, for example, since the most significant bit of a row address is disabled, if an alternate access is merely performed in the same way as at the time when a normal operation is performed, even a word line without a defect will be regarded as the source of replacement, and thus the problem will arise in which word lines without a defect will no longer be selected at the time when a refresh operation is performed.
To solve this problem, a method may be considered that activates all word lines that are the source of replacement and that are to be replaced irrespective of whether or not there is a replacement at the time when a refresh operation is performed. However, according to this method, since even defective word lines are activated although there is no need to activate them, there is the problem in which electric current consumption will increase at the time when a refresh operation is performed. Moreover, since it is necessary to enable both an address corresponding to a word line that is the source of replacement and an address corresponding to a word line that is to be replaced, in a case where addresses are divided into a plurality of portions and decoded (predecoded), an unintended word line may be activated.
For example, when a case is considered in which a word line that is not being replaced is selected by means of a first mat address and a first word line address, and a word line that is to be replaced is selected by a second mat address and a second word line address, it is found that the first word line address is enabled with respect to the second mat address and the second word line address is enabled with respect to the first mat address. Thus, a case arises in which two word lines are activated within the same memory mat. In that case, data is destroyed.
Thus, when simultaneously activating more word lines at the time when a refresh operation is performed than at the time when a normal operation is performed, there has been a problem with respect to the method of handling a replacement operation when a refresh address is the address of a defective memory cell or a defective word line.